The paper describes a VLSI design methodology for the implementation of analog artificial neural networks. Analog VLSI circuit techniques offers area-efficient implementation of the functions required in a neural network such as multiplication, summation and Sigmoid transfer function. However, the analog circuits are sensitive to the problems of process variation, device matching, and cascadeability. For this reason, special attention must be given to the limitations of the MOS transistor and to the design techniques. As result, in analog neural hardware the high accuracy and linearity found in digital implementations is traded off for the simplicity, speed, silicon area and interconnectivity found in analog circuits. The smaller linearity of the synapses based on four quadrant analog multipliers can be compensated by increasing the design effort at the circuit and layout level. The multipliers utilised in the actual implementation consists of four quadrant CMOS analog multipliers based on voltage resistors (VCR). For the VLSI architecture of the neural network system, a description of each analog circuit block is provided. The circuits presented were designed in a 2 *m CMOS process with two layers of metalization and two layers of polysilicon. The architecture is well suited for descent based learning algorithms such as Back Propagation and Weight Perturbation.