The power consumption problem in portable and wireless digital equipment is
the limiting factor for such systems today. While it may be reduced by
careful power management at the system level, the computational complexity
of the signal processing tasks will be limited by the *energy needed per
computation*. In this paper, we have studied 5 different circuits for a
computational element, the important full adder primitive. Since the dynamic
power consumption in CMOS is proportional to Vdd^2, low-voltage operation
of the circuits is important. Four of the circuits are working down to
Vdd=1.1 V for this standard CMOS process, which means that the circuits may
be supplied by one rechargeable battery cell. We show, however, that for a
given throughput, there exists an optimum supply voltage Vdd=3Vt , giving
the minimum total power dissipation, if parallelism and pipelining can be
used. This is illustrated for the 5 full adder circuits, based on simulation
data and measurements. The circuits obtain this minimum at Vdd ~ 2.2-2.4V
corresponding to 3Vt for a standard CMOS process. The best full adder
circuit, SRPL2, dissipates about 30% of the power, but is twice as fast, as
a CMOS standard cell library solution at 2.4V. Using architecture-based
scaling [CSB92] at this supply voltage, the SRPL2 alternative will be about
8 times more power efficient, while requiring half the area.